1. Field of the Invention
The present invention relates to a memory system used for a picture display device or the like, and more particularly to a memory system adapted for realizing fast access to the desired bits within a word.
2. Description of the Prior Art
When making access (writing or reading) to a memory for data (e.g., picture dots) which constitutes a figure or a letter to represent a variety of figures and letters in a picture display, the number of dots that are accessed at one time varies depending upon the kind of figure. For example, in displaying a letter, a picture image, or the like, it is desired to access all the dots that make up the letter or the picture image at one time. On the other hand, in displaying a geometrical figure such as a straight line, a circle, or the like, it will be easier for a human observer to view it as being described gradually one dot at a time. Now, although there is available a prior art memory device which is capable of giving access to a word made up of a plurality of bits corresponding to one address, the number of accessible bits is fixed. Because of this, when an access is desired to a width which is smaller than the fixed bit width, it has been necessary to read out the entire bits within the word once, rewrite only the portion of the desired width, and write in again the whole thing without touching the other portions. In short, this method has a disadvantage of requiring a complicated procedure for rewriting and a longer time for processing. On the other hand, it is possible to construct a memory so as to allow access one bit at a time. However, such an arrangement also has a disadvantage of requiring a long time since the access is possible only one bit at a time. As a device which eliminates such disadvantages, there has been known one as is disclosed in Japanese Patent Publication No. 57-179982. This memory device is adapted for rewriting all of the bits or a part of the bits in a word by dividing the word into groups of n bits, and comprises a memory circuit with write or read units of n bits (n=1, 2, 3, . . . ), a data input terminal with N bits (N=l.times.n, l=2, 3, 4, . . . ), a data selection circuit which selects n bits from the N-bit data that are inputted through the input terminal, an input terminal for a control signal which indicates together with the write indication signal whether all of the N bits or n bits of the N bits are to be rewritten, an input terminal for an address information for the memory circuit, an internal address generating circuit which outputs l kinds of data selection signals to the data selection circuits based on the control signal input through the input terminal and outputs the write indication signal and l kinds of internal address (the addresses for the n bits in the word) to the memory circuit for l times as well and an output terminal. In the above memory circuit, the N bits in the word with address i are divided into groups of n bits which are memorized at the l addresses at i+0, i+1, . . . , i+(l-1). First, when all of the N bits in the word with address i are to be rewritten, the internal address generating circuit outputs sequentially l kinds of internal addresses and l kinds of data selection signals to the memory circuit and the data selection circuit based on the control signal at the input terminal respectively, and outputs the write indication signal to the memory circuit for l times as well, which accomplishes the rewriting of all of the N bits with address i in the memory circuit. However, even in this case where all of the N bits are desired to be rewritten, it takes a longer time and hence is inefficient since the rewriting has to be done sequentially in a group of n bits. When only n bits of the N bits in the word with address i are to be rewitten, the internal address generating circuit outputs, based on the control signal at the input terminal, l kinds of data selection signals and the specified internal addresses in address i that are generated sequentially for l times to the data selection circuit and the memory circuit, respectively, and outputs as well the write indication signal to the memory circuit for l times. In this case, it is very inefficient since the data for the n bits outputted from the data selection circuit are written for l times to the specified n bits in address i of the memory circuit, and only the data for the n bits which were written for the last, that is, the l-th, time are memorized. Moreover, in the example cited in the above, internal addresses, signals, data selection signals, and write indication signals, in addition to the address information, have to be inputted so that the control for their synchronization has also been complicated.